1. Field of the Invention
The invention relates generally to semiconductor devices, and more particularly to an improved integrated circuit comb capacitor.
2. Description of the Related Art
As ULSI integrated circuits scale to smaller dimensions and increased function and circuit density, many electronic functions that were formerly off-chip are now being incorporated on-chip. These then take advantage of fabrication economies as well as reduced electrical signaling distances to become cheaper and add higher system function and higher performance. One family of devices that has been the focus of increased innovation for on-chip integration is BEOL passive devices. Although interconnects themselves are, strictly speaking, also passive devices, that term is conventionally applied to other passive electronic devices such as resistors, capacitors, inductors, and varactors. Although resistors and capacitors have always been integrated in the FEOL for transistor logic circuits, those FEOL passive devices suffer from voltage nonlinearities and unwanted parasitic impedances that render them not useful for many types of analogue circuits such as for RF or wireless applications. Inductors in general can only obtain useful parameters when integrated in the BEOL wiring levels.
For BEOL capacitors, the most common type of device is the planar metal-insulator-metal (MIM) parallel plate capacitor. This requires one or more added photomask levels to fabricate lower and upper electrode plates, the capacitor dielectric, and contacts to the plates. These are usually distinct from other interconnects and via contacts formed in the same wiring level. The disadvantages of MIM capacitors is the number of added masks and process steps, the asymmetry in parasitic capacitive coupling to the substrate of the upper and lower electrodes, the limited dielectric reliability at the small thicknesses needed for sufficient capacitance density, and the chip real-estate occupied which often requires exclusion of wiring from areas directly below the MIM capacitor.
Another type of BEOL capacitor is the interdigitated comb-comb type; this is comprised of multiple line-to-line capacitor fingers connected in parallel (so their capacitances add) with alternating bias between each pair of lines. The devices rely on standard wiring sidewall depths and minimum interline spacings to maximize their capacitances. These dimensions are such that a single-level comb-comb capacitance density is much smaller per unit layout area than what is possible with the MIM capacitors, and as well the typically larger dimensional deviations associated with the interconnect thicknesses and spacings may make it more challenging to meet design specifications. On the other hand, the interdigitated integrated circuit comb capacitor requires no additional photomasks or processing steps (as long as the same interline dielectric is used) and has no asymmetry in parasitic coupling to the substrate for the two electrodes.
FIG. 1 shows an integrated circuit comb capacitor 150 created in accordance with the prior art. Therefore, in accordance with the prior art, the capacitor electrodes 150a have the same depth and spacing between neighboring capacitor electrodes 150a as interconnects 160 formed in the same wiring level. The capacitor is preferably made from copper damascene embedded in a low-k dielectric (∈) material 102 such as SiCOH organosilicate glass. The capacitor electrodes 150a are characterized by their lengths (into/out of page), widths, depths, spacings, and if trapezoidal, their sidewall angles (α). When energized as in an active IC circuit, the successive electrodes 150a are typically biased in an alternating sense such as Vdd (+) and Ground (−) or with an AC signal to perform the capacitor function.
More recently, an enhancement to the integrated circuit comb capacitor 150 has been described which solves some of the aforementioned problems. Called the vertical parallel plate (VPP) capacitor, this is comprised of multilevel stacks of interdigitated integrated circuit comb capacitors 150. With VPP capacitors, areal capacitance densities equal those of the MIM devices, there are still no added photomasks or processing steps, and there is still no asymmetry in parasitics for both electrodes. In addition, when multiple levels are combined, the statistical variations in linewidth and spacing dimensions tend to average out so that more uniform results, better matching, and tighter tolerances may be obtained from chip to chip and wafer to wafer. The disadvantage is the number of levels and layout area required to achieve a given capacitance.
This disadvantage becomes larger for integration of the VPP capacitor in modern low-k BEOL levels, where capacitance density decreases directly in proportion to the decrease in the interline and interlevel dielectric constants. This disadvantage does not apply to the MIM case which uses a separate capacitor dielectric. However, the other disadvantages of the MIM capacitor remain for integration in low-k BEOL. In addition, with CMOS scaling driving reductions in all wiring dimensions, the interlevel BEOL vertical spacings decrease while the MIM thickness does not, such that fabrication becomes difficult or impossible due to excessive topography over the MIM areas.
Given the above discussion, there is still a need to obtain larger capacitance densities especially for low-k BEOL integrated capacitors, while adding minimal masking levels, minimizing capacitance tolerances, and preserving symmetry in electrode-substrate coupling parasitics.
What is needed in the art is an improved low-k BEOL integrated circuit comb capacitor, which minimizes capacitance tolerances and preserves symmetry in parasitic electrode-substrate coupling and that is created with a minimum of additional masking levels or process steps.